Standard Cell Library

The Optimization Method of Register in 0.13 μ m Standard Cell Library

0.13μm标准单元库中寄存器的优化方法

Design of Evaluation Circuit for a CMOS Standard cell Library

一种CMOS标准单元库的评估电路设计

A Low Supply Noise Output Driver for Standard Cell Library

一种适用于标准单元库的低电源噪声输出驱动器

Decomposition of Multilevel Logic Functions Based on the Standard Cell Library

基于标准单元库的多级函数分解

The design is accomplished using Top-down design flow and standard cell library method .

整个系统采用标准单元设计方式和Top-Down自上而下的设计方法。

The Methodology of Developing 1.2 μ m CMOS Standard Cell Library

1.2μMCMOS标准单元库的开发方法

Research on the Technique of GaAs ASIC Standard Cell Library

GaAsASIC标准单元库建库技术研究

Standard cell library is getting bigger and bigger , some have been over 500 units .

但同时标准单元库也变得越来越大，有的多达500多个。

The standard cell library is a foundation to ASIC Design , its quality and performance is vital to ASIC Design .

标准单元库是ASIC设计的基础，它的质量和性能对ASIC设计来说至关重要。

The experimental results demonstrate that the DPA-resistant standard cell library can counteract DPA attacks effectively .

实验结果表明，这种标准单元库能够很好地起到防DPA攻击的作用。

In order to take into account the performance and design time , semi-custom design method based on standard cell library is used to implement multiplier .

为了兼顾乘法器的性能和设计时间，通常使用基于标准单元库的半定制设计方法。

As the foundation of modern digital circuit design , the Standard Cell library and its performance improvement has tremendous effect on the capability of digital circuit .

标准单元库作为数字电路设计的基础，其性能的改善对整体电路性能的提高有着十分重要的作用。

In Chapter 2 , an approach is proposed for building gate delay model and interconnect delay model by extracting data from the standard cell library .

第二章：提出了从库中提取数据建立门延模型和连线时延模型的方法。

Experimental results show that the semi-custom design methodology based on standard cell library extension can improve circuit performance effectively , which is especially appropriate for designs with large loads .

实验结果表明，基于标准单元库扩展的半定制设计方法可以有效提升电路的性能，这种方法尤其适用于电路负载过大的情况。

A non-clock delay-ring A / D converter is presented , which is based on standard cell library and not sensitive to process variation .

提出了一种无需外部时钟、可以部分抵消工艺偏差、基于标准单元的延迟环A/D变换器。

The integration of USB IP core into an MP3 decoding chip is presented . The design was implemented on the platform of 0.18 μ m standard cell library .

将USBIP核集成到一块MP3解码芯片上，其设计在0.18μm工艺平台中进行。

Traditional asynchronous integrated circuit design uses full custom design with low efficiency , because the asynchronous circuit implementation needs novel circuit structures which do not exist in traditional standard cell library .

为了以新颖的电路结构实现异步集成电路中的特殊功能，一般的异步集成电路设计都采用全定制的方法，设计效率不高。

The results of simulation at the level of algorithm and using 0.25 μ m standard cell library show that the designed equalizer can effectively eliminate inter-symbol interference ( ISI ) .

所设计的均衡器经过算法级仿真和带0.25μm标准工艺库仿真，结果表明能有效消除码间干扰（ISI）。

It could be concluded from the practical experiment that the semi-custom design method based on extended standard cell library could shorten the critical path delay and improve circuit frequency effectively in mainstream technology design .

经过实验仿真和验证，主流工艺下基于可扩展标准单元的半定制电路设计方法能够有效地缩短关键路径延时，提升电路主频性能。

A methodology to design and characterize a DPA-resistant standard cell library is introduced in this paper , and then the designed standard cells are used to implement an S-box of DES .

给出了一个功耗恒定标准单元库的设计实现方法，并利用该标准单元库实现了DES密码算法中的S-盒。

The RSA coprocessor has been implemented by using 0.5 μ m CMOS standard cell library . The coprocessor has 14 K gates count and 3 mm ~ 2 die size with a maximum clock frequency 40 MHz , which takes about 375 ms to encrypt / decrypt 1024-bit data .

利用0.5μMCMOS标准单元库实现了该RSA协处理器，约折合14K（210）等效门，面积约3mm2，最高工作频率40MHz，完成1024位RSA加/解密运算需时375ms。

Second , according to the feature of trap logic unit , we design the high driving capability , special logic and high-speed standard cells , which enhance the ability of standard cell library to support the trap logic unit , and it optimizes the critical path delay greatly .

其次，针对中断逻辑部件的特点，定制设计了大驱动、特殊逻辑和高速的标准单元，增强了标准单元库对中断逻辑部件的支持能力，缩短了关键路径的延时。